[ updated on 22 August 2008]This article addresses the multistage amplifier designing with the given design specification.If you are not interested in multistage amplifier designing you are on the wrong page and can stop reading.

• If you are not familiar with basic principles of frequency response or not in possession of Microelectronic Circuits by Sedra and Smith, I would humbly ask you to leave to avoid any dissatisfaction.
• This is tested in simulation and design, and hence if you follow the guide lines accurately you won't run into any trouble.

The problem

• Designing of an amplifier with the following specifications
• Gain 20 dB to 60 dB
• Input impedance > 5K
• Output impedance < 100
• Bandwidth 100Hz – 3 MHz (can't help folks from groups 1, 6, 11, 16)
• This design should work perfectly with a source impedance of 600 and load impedance of 10K

DesignThe solution explained below gives the designing. Apologies, folks who were fortunate enough to get 20Hz – 20kHz. Achieving such a lower cutoff  (20Hz) is hard with a RE resistor across 40ohms resistor in output stage. However, it is possible through a small modification.As many others I also thought amplifier designing is hard. However I was wrong and it is damn simple with proper analysis and Orcad (those who are not familiar with Orcad can refer this). We need an output stage to have an output resistance as low as 100 ohms, while maintaining enough amplification. To obtain a gain of around 40dB, we need an amplification stage (CE amplifier).In CE amplifier we get moderate input impedance and by maintaining a small Ib (Ri = gm / ib) input impedance can be raised above 5K. In the design provided it is 6.25K. Hence, we wouldn’t need a separate input stage.The design uses the popular BC109B transistor with resistors and capacitors of standard values with the power supply of 9v

Design procedures (stage 1)

• I decided to give Vc 5v and Ve 2v to get a large swing in the signal.(keep in mind Vce <> Vcc/3 - Vcc/2 requirement - from ALs knowledge)
• Resistors are selected to give an Ic of 1mA
• Ratio between Rbs are selected to maintain 2.65v (2.0 + 0.65) at B.
• However Rbs of input stage were selected to be as high as possible to avoid any dependence input resistance (small signal analysis) on Rbs.
• By pass capacitor is chosen to provide the required frequency range as explained in the next section. 

Design procedures (stage 2)

• Rbs of output stages are selected to provide the required frequency range as explained in the next section.
• Coupling capacitors are chosen to be of very high value (500u) and reduced gradually to the safe level by avoiding any cutoff (again you could utilize your AL knowlege  that coupling capacitors remove DC components or in other words lowfrequency harmonics, folks improvising this circuit for 20Hz must be warned). 
• Re is not bypassed with any capacitors to avoid any possible cutoffs that could occur.

Tuning the design to match the required frequency rangeThe circuit provided can be tuned for upper and lower cutoff frequencies independently. That is they can be tuned without affecting each other. This is achieved by controlling the lower cutoff at the input stage and the upper cutoff at the output stage.Please follow the order to get optimum results.

1.  Upper cutoff frequency is primarily desided by the property of the transistor (Rpi, Ru, Cpi, Cu).
   1. However Fh = 1 /(2*pi*R’ * C’)
   2. where C’ is dependent on load resistance and amplification or simply gmRl which is generally equal to the voltage drop across Rc.
   3. Hence it can be controlled by the input stage amplification or load resistance (output stage input resistance affects the input stage load resistance).
   4. However to make the adjustments independent, I chose input stage load resistance ie Rbs of output stage (instead of chosing gm or Rc or the product which I maintain constant - see the description above) .
   5. Although ratio of Rbs are fixed by the Vb required, we can change the values to match Fh.
   6. By adjusting Rbs of output stage (ie increase them to decrease Fh and vice versa) while maintaining the ratio, Fh (upper cutoff frequency ) can be set.
2. Lower cutoff frequencies are decided by the poles created by the coupling and by pass capacitors.
   1. However it is the bypass capacitor has the pole of the highest frequency, hence it is chosen for controlling the lower cutoff frequency (see the discussion in Sedra n Smith 5.9.3 and figure 5.73).
   2. By adjusting Re of input stage (ie increase it to decrease Fl and vice versa) Fl – lower cutoff can be set. 

Few wordsI hope this tiny article together with the circuit diagrams and frequency responses will help you in designing the amplifier. You are welcome to make changes and give suggestions to improve.The prerequisite to solicit any help on this article is to digg!